In all the control schemes of switching regulators, constant ON-time (COT) control scheme is widely used because of its many advantages. In COT control scheme, loop compensation is not needed, so the design of the switching regulator is simple. Moreover, the transient response of the switching regulator is fast since no error amplifier is needed to adjust the voltage. In addition, if the switching regulator operates in pulse frequency modulation (PFM) mode at light load, and switches to pulse width modulation (PWM) mode at heavy load, the transition between the PFM mode and PWM mode is also smoother by using the COT scheme. Because the COT control scheme has the foregoing advantages but not limited to them, it can be used widely in the applications of the power control for switching regulators.
In most applications, a comparator is used for comparing a feedback voltage VFB reflecting the output voltage VOUT of the switching regulator with a reference voltage VREF. Based on the comparison result, the switching regulator controls a power stage to adjust the output voltage VOUT of the switching regulator.
FIG. 1 illustrates a prior buck switching regulator 10. As shown in FIG. 1, a feedback circuit consisting of resistors RD1 and RD2 is used to convert the output voltage VOUT of the switching regulator 10 into the feedback voltage VFB that is provided to the inverting input terminal of the comparator COMP. The non-inverting input terminal of the comparator COMP is configured to receive an actual reference voltage VR provided by a reference voltage source VREF. If the output voltage VOUT decreases, the feedback voltage VFB will also decrease. When the feedback voltage VFB is decreased to be smaller than the actual reference voltage VR, the comparator COMP generates a high level signal to set the flip-flop 14. The high side switch Q1 is turned on and the low side switch Q2 is turned off. The output voltage VOUT increases.
After a constant ON-time TON, a high level signal is generated by a COT generator 13 to reset the flip-flop 14. The high side switch Q1 is turned off and the low side switch Q2 is turned on. The feedback voltage VFB as well as the output voltage VOUT deceases. When the feedback voltage VFB is decreased to be smaller than the actual reference voltage VR, the comparator COMP generates a high level signal to set the flip-flop 14, then the output voltage VOUT increases. The foregoing operation is repeated in the next working period.
FIG. 2 illustrates several working waveforms of the buck switching regulator 10 shown in FIG. 1. As shown in FIG. 2, the several waveforms are a switching signal SW, an equivalent series resistance (ESR) ripple, a capacitor ripple CAP of the output capacitor COUT and the output voltage. Because of the existence of the ESR ripple and the capacitor ripple CAP, the comparator COMP actually compares the valley of the output voltage with the reference voltage VREF in each working period. Suppose the relationship between the feedback voltage VFB and output voltage VOUT is:VFB=K×VOUT  (1)wherein K is the scaling factor. And suppose the set value of the output voltage VOUTS is:
                              V          OUTS                =                              1            K                    ×                      V            REF                                              (        2        )            There exists a voltage error VOUTE between the actual output voltage VOUTR and the set value of the output voltage VOUTS. For applications with small output voltage, such as DSP/CPU/Memory power supplies, the voltage error VOUTE generated by the output voltage ripple will seriously affect the output voltage accuracy of the switching regulator. For example, if the set value of the output voltage VOUTS is 1V and the amplitude of the output voltage ripple is 50 mV, the actual output voltage VOUTR is 2.5% higher than the set value of the output voltage VOUTS.